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ISL97671A
Configuration Register (0x08)
The Configuration Register provides many extra functions that
users can explore in order to optimize the driver performance at
a given application.
A BstSlewRate bit allows users to control the boost FET slew rate
(the rates of turn-on and turn-off). The slew rate can be selected
to four relative strengths when driving the internal boost FET. The
purpose of this function is to allow users to experiment with the
slew rate with respect to EMI effect in the system. In general, the
slower the slew rate is, the lower the EMI interference to the
surrounding circuits; however, the switching loss of the boost FET
is also increased.
The FSW bit allows users to set the boost converter switching
frequency between 1.2MHz and 600kHz. The VSC bit allows
users to set the LED string short circuit threshold VSC to 7.2V or
disable it.
The bit assignment is shown in Figure 34. The default value for
Register 0x08 is 0x1F.
Output Channel Mask/Fault Readout
Register (0x09)
This register can be read or written. It allows enabling and
disabling each channel individually. The bit position corresponds
to the channel. For example, Bit 0 corresponds to Ch0 and bit 5
corresponds to Ch5 and so on. A 1 bit value enables the channel
of interest. When reading data from this register, any disabled
channel and any faulted out channel will read as 0. This allows
the user to determine which channel is faulty and optionally not
enabling it in order to allow the rest of the system to continue to
function. Additionally, a faulted out channel can be disabled and
re-enabled in order to allow a retry for any faulty channel without
having to power-down the other channels.
The bit assignment is shown in Figure 35. The default for
Register 0x09 is 0x3F.
REGISTER 0x08
CONFIGURATION REGISTER
RESERVED
Bit 7 (R/W)
RESERVED
Bit 6 (R/W)
BIT5
Bit 5 (R/W)
BIT4
Bit 4 (R/W)
BIT3
Bit 3 (R/W)
FSW
Bit 2 (R/W)
RESERVED
Bit 1 (R/W)
VSC
Bit 0 (R/W)
BIT ASSIGNMENT
BstSlewRate[1:0]
FSW
VSC
REGISTER 0x09
BIT FIELD DEFINITIONS
Controls strength of FET driver. 00 - 25% drive strength, 01 to 50% drive strength,
10 -75% drive strength, 11 to 100% drive strength.
2 levels of Switching Frequencies (1 = 1,200kHz, 0 = 600kHz)
Enable / Disable Short Circuit Protection (0 = disabled, 1 = 7.5V minimum)
FIGURE 34. DESCRIPTIONS OF CONFIGURATION REGISTER
OUTPUT CHANNEL REGISTER
RESERVED
Bit 7 (R/W)
RESERVED
Bit 6 (R/W)
CH5
Bit 5 (R/W)
CH4
Bit 4 (R/W)
CH3
Bit 3 (R/W)
CH2
Bit 2 (R/W)
CH1
Bit 1 (R/W)
CH0
Bit 0 (R/W)
BIT ASSIGNMENT
CH[5..0]
23
BIT FIELD DEFINITIONS
CH5 = Channel 5, CH4 = Channel 4 and so on
FIGURE 35. OUTPUT CHANNEL REGISTER
FN7709.3
November 30, 2012
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